1. For the schematic entry Cadence tool, give the bind keys associated with “zoom”, “fit schematic to window”, “start drawing a wire”, “moving a component”, and “query component” parameters.
2. Name and briefly describe four types of cell views (eg. layout, extracted, schematic, etc.).
3. Include a copy of the simulation output in your submission (a screen grab is fine). Create a truth table for the gate-level circuit from the simulation output.
4. Write the boolean expression corresponding to the gate-level schematic. Show that the simulated waveforms match the truth table.
5. Re-write the boolean expression from Question #4 into a new form (use boolean algebra, DeMorgan’s Theorem, etc.), and revise your schematic to implement the new boolean expression. Include a picture of your updated schematic in your submission.
6. Re-simulate your cell, which should now contain two different implementations of the logic [removed]one that I gave you in the video above, and one that you derived by rewritingthe boolean expression). Show your results.
7. Compare the outputs of the two logic implementations. Do they match? If not, explain any differences that you find.
8. Estimate the required layout area for the given logic circuit and the one you derived. Compare the required areas and comment on the logic expressions versus the required layout areas.
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